Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits

US5867036A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventor

• Rochit Rajsuman · San Jose, US

Key dates

• Filing date: May 29, 1996
• Grant date: Feb 2, 1999
• Expiry date: May 29, 2016

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318541
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic include two registers that surround the Domino logic to allow that logic to be tested. One register receives an input test vector, loaded directly through a primary set of inputs or by a serial scan chain if the register inputs are not directly accessible. The second register latches the results of the test vector application. The register contents can either be read directly through a primary set of outputs if there is no static CMOS logic between the register outputs and a primary set of circuit outputs, or scanned out of the second register using a serial scan chain. Domino scan flip-flops, which reduce transistor count over conventional static scan flip-flops, can be used in the Domino logic as sequential elements to implement multiple logic functions. These scan flip-flops can be serially connected as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. Domino scan flip-flops allow all of the nominal logic to be tested in conjunction with the two registers. A Domino clock used to drive the Domino lo…