Apparatus and method for accessing a branch target buffer
US5867698A · kind A · utility
9Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1996 |
| Grant date | Feb 2, 1999 |
| Priority date | — |
| Expiry date | Oct 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.