Method and structure for constraining the flow of incapsulant applied to an I/C chip on a substrate
US5869356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1998 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Mar 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.