Single layer integrated metal process for metal semiconductor field effect transistor (MESFET)
US5869364A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1996 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Jul 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state-of-the-art electrical performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.