Electrostatic discharge protection circuit having eprom
US5869873A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 1998 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | May 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic discharge protection circuit comprises a PNP transistor, a NPN transistor, and an erasable programmable read only memory. The PNP and NPN transistors have an emitter, a base, and a collector, respectively. The PNP transistor is configured with its emitter connected to the pad, its base connected to the collector of the NPN transistor, and its collector connected to the base of the NPN transistor. The emitter of the NPN transistor is connected to a circuit node. The erasable programmable read only memory is configured with a drain connected to the base of the PNP transistor, a source connected to the circuit node, and a control gate coupled to the circuit node. When electrostatic discharge stress occurs at the pad, the erasable programmable read only memory enters breakdown to be programmed and triggers the conduction of the transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.