Method for aligning semiconductor wafer surface scans and identifying added and removed particles resulting from wafer handling or processing
US5870187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 1997 |
| Grant date | Feb 9, 1999 |
| Priority date | — |
| Expiry date | Aug 8, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N21/9501
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An automated method for aligning wafer surface scan maps and locating defects such as particle contaminant distributions on a wafer surface. More specifically, the invention is an automated method for locating added and removed contaminants and other defects on a semiconductor wafer surface after the wafer has undergone wafer-handling and/or processing. A second data set of a second scan of a wafer surface is misalignment-corrected to a first coordinate system of a first scan of the wafer surface. Thereafter, a final match is made between a first data set of the first scan and the misalignment-corrected data of the second scan. Non-matching locations in the misalignment-corrected data of the second scan represent added defects on the surface of the wafer. Non-matching locations in the base data of the first scan represent removed defects from the surface of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.