System and method for performing multiway branches using a visual instruction set
US5872965A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1997 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Jun 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/324
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An innovative method and system of performing multiway branch operations on a microprocessor architecture which supports single instruction multiple data (SIMD) operations is provided. A computer processor includes a branch condition register, a graphic status register, a displacement register, a branch offset register, a program counter register and circuit logic responsive to a multiway branch opcode. Bitwise AND logic coupled to the branch condition register and the graphic status register performs a bitwise logical AND between a mask contained in the branch condition register and multiple comparison results contained in the graphic status register. An output port from bitwise logical AND is coupled to a constant array and selects a set of constant values based on the bitwise logical AND result value. A shifter logic coupled to the branch offset register and the displacement register bitwise left shifts the displacement value stored in the displacement register a predetermined amount based upon the value in the branch offset. The shifter logic is also coupled to receive a constant value from the constant array which is added to the shifted result by concantenating the constant v…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.