Method and apparatus for transmitting memory requests by transmitting portions of count data in adjacent words of a packet
US5872996A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 1997 |
| Grant date | Feb 16, 1999 |
| Priority date | — |
| Expiry date | Sep 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/376
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten multiplexed transmission lines, identified as BusCtl and BusData 8:0!. The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible. The type of memory access is arranged over a plurality of clock cycles, placing the more critical bits first. The count of blocks of data requested is arranged to minimize the number of bit positions in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.