Small contacts for ultra large scale integration semiconductor devices without separation ground rule
US5874359A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating very narrow contacts on semiconductor substrate for increasing the packing density of devices on Ultra Large Scale Integration (ULSI) circuits was achieved. The method involves using conventional photolithographic techniques and anisotropic plasma etching to etch openings in a conducting layer and partially etch into an underlying planar insulating layer that covers and isolates the devices and device contact areas. Another conformal conducting layer is deposited on the substrate and in the openings and then etched back to form sidewall spacers in the openings. Using the original conducting layer and the sidewall spacers as an etch mask, the planar insulating layer is anisotropically etched within the sidewall spacers to form very narrow (small) contact opening to the desired device contact areas. Still another conducting layer is then deposited to fill the very narrow contact openings making electrical contact to the device contact areas, and then the conducting layers are patterned to form the next level of connecting metallurgy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.