Semiconductor device having a high breakdown voltage
US5874768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1997 |
| Grant date | Feb 23, 1999 |
| Priority date | — |
| Expiry date | Nov 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.