Method of making MOS-gated semiconductor devices

US5877044A · kind A · utility

Assignee

• HARRIS CORPORATION · US

Inventors

• John Manning Savidge Neilson · King of Prussia, US
• Christopher Boguslaw Kocon · Mountain Top, US
• Richard Stokes · Shavertown, US
• Linda S. Brush · Smethport, US
• John L. Benjamin · Smethport, US
• Louise Skurkey · Conyngham, US
• Christopher L. Rexer · Mountain Top, US

Key dates

• Filing date: Mar 11, 1997
• Grant date: Mar 2, 1999
• Expiry date: Mar 11, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393

Abstract

A gate electrode control structure of an MOS-gated semiconductor device includes four doped regions including a first (source) region forming a first P-N junction with an enclosing composite region comprising a second, lightly doped (channel) region wholly enclosing a third heavily doped (body) region partly enclosing the first region, and a fourth (drain) region forming a P-N junction with the third region. The gate electrode control structure is fabricated using known gate electrode self-alignment doping processes but wherein, in the process for forming the third heavily doped region, a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision.