Parallel hierarchical timing correction
US5877965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1996 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Jun 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for performing timing correction on a hierarchical integrated circuit design comprising the steps of forming a hierarchical integrated circuit design, applying a hierarchical timing tool to the entire circuit hierarchy, applying a timing correction algorithm to improve timing of the design as measured by the hierarchical timing tool; and applying a parallel timing management tool to multiple applications of the hierarchical timing tool and the timing correction algorithm. Also described is an information handling system including means for implementing the parallel hierarchical timing correction method of the present invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.