Todd E. Leonard
32Patents
7h-index
46Co-inventors
69Inventor score
Filing activity: Jun 24, 1996 → Aug 14, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6498782B1 | Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation | Electricity | 35 | Expired |
| US8793365B2 | Environmental and computing cost reduction with improved reliability in workload assignment to distributed computing nodes | Emerging Cross-Sectional Technologies | 16 | Active |
| US7483806B1 | Design structures, method and systems of powering on integrated circuit | Emerging Cross-Sectional Technologies | 15 | Active |
| US9230940B2 | Three-dimensional chip stack for self-powered integrated circuit | Emerging Cross-Sectional Technologies | 12 | Active |
| US7225387B2 | Multilevel parallel CRC generation and checking circuit | Electricity | 9 | Expired |
| US5877965A | Parallel hierarchical timing correction | Physics | 8 | Expired |
| US6686086B1 | Battery reclamation system | Emerging Cross-Sectional Technologies | 8 | Expired |
| US7715323B2 | Method for monitoring BER in an infiniband environment | Electricity | 7 | Active |
| US8618833B1 | Source series terminated driver circuit with programmable output resistance, amplitude reduction, and equalization | Electricity | 6 | Active |
| US7941772B2 | Dynamic critical path detector for digital logic circuit paths | Physics | 6 | Active |
| US7716007B2 | Design structures of powering on integrated circuit | Emerging Cross-Sectional Technologies | 5 | Active |
| US6765911B1 | Communications adapter for implementing communications in a network and providing multiple modes of communications | Electricity | 5 | Expired |
| US8132136B2 | Dynamic critical path detector for digital logic circuit paths | Physics | 4 | Active |
| US7103832B2 | Scalable cyclic redundancy check circuit | Electricity | 4 | Expired |
| US8396106B2 | System and method for improving equalization in a high speed serdes environment | Electricity | 4 | Active |
| US8291357B2 | On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations | Electricity | 4 | Active |
| US8347019B2 | Structure for hardware assisted bus state transition circuit using content addressable memories | Physics | 3 | Active |
| US8136010B2 | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs | Electricity | 3 | Active |
| US8016482B2 | Method and systems of powering on integrated circuit | Physics | 3 | Active |
| US7898286B2 | Critical path redundant logic for mitigation of hardware across chip variation | Physics | 3 | Active |
| US7823017B2 | Structure for task based debugger (transaction-event-job-trigger) | Physics | 3 | Active |
| US7869379B2 | Method for monitoring channel eye characteristics in a high-speed SerDes data link | Electricity | 3 | Active |
| US8989313B2 | Adaptable receiver detection | Electricity | 2 | Active |
| US7886210B2 | Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs | Electricity | 2 | Active |
| US7904872B2 | System-on-chip (SOC), design structure and method | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.