Data structure to support multiple transmit packets for high performance
US5878028A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1996 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Jun 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40013
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data structure to provide high performance in the transmit portion of an ethernet controller. The data structure includes the data to be transmitted, the STATUS information of the data to be transmitted, and the DESCRIPTOR information of the data to be transmitted. The data is organized in 8-bit bytes in 32-bit rows, the 32 bit STATUS information is organized in four 8-bit bytes in a 32 bit row, and the 32 bit DESCRIPTOR information is organized in four 8-bit bytes in a 32 bit row. A one-bit tag field is associated with each of the rows and a 1 in the tag field indicates that the end-of-packet is located in the row associated with that tag. The lower four bits of a STATUS byte contains information indicating which byte in the row contains the end-of-packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.