Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring
US5878208A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1996 |
| Grant date | Mar 2, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine address traces, data addresses and data during the trace, if the initial architectural state is known. The difficulty in reconstructing an instruction trace from monitored bus traffic can be decreased substantially if more definitive information regarding the actual instruction sequence can be obtained. An internal performance monitor within the processor system is utilized to detect each occurrence of the execution of a specified number of instructions and each occurrence of the execution of a specified number of some specific type of instruction such as load instructions or store instructions and generate an output in response to each such occurrence. This information, in addition to each detected occurrence of an external interrupt, is then utilized in combina…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.