Inventor · Round Rock, TX, US

William J. Starke

311Patents
23h-index
139Co-inventors
93Inventor score

Filing activity: Dec 6, 1994 → Dec 19, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6009261A Preprocessing of stored target routines for emulating incompatible instructions on a target processor Physics 431 Expired
US5560013A Method of using a target processor to execute programs of a source architecture that uses multiple address spaces Physics 217 Expired
US5577231A Storage access authorization controls in a computer system using dynamic translation of large addresses Physics 152 Expired
US6075937A Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation Physics 45 Expired
US5878208A Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring Physics 40 Expired
US7469318B2 System bus structure for large L2 cache array topology with different latency domains Emerging Cross-Sectional Technologies 40 Active
US6643763B1 Register pipe for multi-processing engine environment Physics 38 Expired
US5894575A Method and system for initial state determination for instruction trace reconstruction Physics 38 Expired
US6345342B1 Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line Physics 38 Expired
US6694427B1 Method system and apparatus for instruction tracing with out of order processors Physics 35 Expired
US7272773B2 Cache directory array recovery mechanism to support special ECC stuck bit matrix Physics 32 Expired
US6785774B2 High performance symmetric multiprocessing systems via super-coherent data mechanisms Physics 31 Expired
US7047320B2 Data processing system providing hardware acceleration of input/output (I/O) communication Physics 31 Expired
US6704844B2 Dynamic hardware and software performance optimizations for super-coherent SMP systems Physics 30 Expired
US6606666B1 Method and system for controlling information flow between a producer and a buffer in a high frequency digital system Electricity 27 Expired
US7069494B2 Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism Electricity 27 Expired
US7032097B2 Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache Physics 25 Expired
US7228385B2 Processor, data processing system and method for synchronizing access to data in shared memory Physics 24 Expired
US5889947A Apparatus and method for executing instructions that select a storage location for output values in response to an operation count Physics 24 Expired
US6996679B2 Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members Physics 24 Expired
US6629209B1 Cache coherency protocol permitting sharing of a locked data granule Physics 24 Expired
US6421761B1 Partitioned cache and management method for selectively caching data by type Physics 24 Expired
US5809566A Automatic cache prefetch timing with dynamic trigger migration Physics 24 Expired
US7305522B2 Victim cache using direct intervention Physics 23 Expired
US6321306A High performance multiprocessor system with modified-unsolicited cache state Physics 22 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.