Trench random access memory cell and method of formation
US5879971A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
Abstract
A method for forming a random access memory cell within four separate trench regions (106, 108, 110, and 112). One half of the memory cell has a first N-type transistor, which is a latch transistor (500), has a current electrode (101), a current electrode (126), and a gate electrode (114). A second N-type transistor, which is a word-line select transistor (504), has a first current electrode (101), a second current electrode (128), and a gate electrode (116). A P-channel pull up transistor (502) has a first current electrode (103), a second current electrode (124), and a gate electrode (114). The coupling of the electrodes (101 and 103) form a storage node of the one half of the memory cell which is contacted electrically by a conductive contact (140).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.