Method for fabrication of a one gigabit capacitor over bit line DRAM cell with an area equal to eight times the used minimum feature

US5879986A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Janmye Sung · Taipei, TW

Key dates

• Filing date: Feb 27, 1998
• Grant date: Mar 9, 1999
• Expiry date: Feb 27, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A process for fabricating a high density, capacitor over bit line, DRAM cell, using 8F.sup.2 technology, has been developed. The process features self-alignment of a tungsten bit line structure, to polycide word lines, and self-alignment of a capacitor node structure, to both tungsten bit lines, and to polycide word line structures. Self-alignment is accomplished by opening contact holes between polycide gate structures, and between tungsten bit line structures, which are coated with silicon nitride spacers, followed by filling with polysilicon plugs, which in turn contact underlying regions of the semiconductor substrate.