Method of fabricating dynamic random access memory having a stacked capacitor

US5879987A · kind A · utility

Inventor

• Chuan-Fu Wang · Banluliao, TW

Key dates

• Filing date: May 14, 1998
• Grant date: Mar 9, 1999
• Expiry date: May 14, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/318

Abstract

A structure of a capacitor in a DRAM includes: A dielectric layer with a contact window for later connecting use is formed on a substrate. Then, a first-conductive layer is formed over the dielectric and is coupled to either the source or the drain of a TFET through the contact window. Subsequently, a number of insulating layers and second-conductive layers are superposed alternatively together to form a stacked layer. By using the space occupied by the insulating layers, a number of third-conductive layers replacing the inner portion of the insulating layers are formed in between the second-conductive layers. After removing the insulating layers between the second-conductive layers, a structure of a horn-like in a sectional view is formed. The first-conductive layer, the second-conductive layers and the third-conductive layers are coupled together to act as a lower electrode of the capacitor. Then, a dielectric thin film is formed over the lower electrode. And then, the fourth-conductive layer is formed over the dielectric thin film to act as an upper electrode.