Planarization of a non-conformal device layer in semiconductor fabrication
US5880007A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.