Low and high voltage CMOS devices and process for fabricating same
US5880502A · kind A · utility
32Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1996 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.