Energy absorbing structures to prevent damage to an integrated circuit
US5880528A · kind A · utility
7Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides in one embodiment thereof an integrated circuit (IC). The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The IC also includes a first guard ring formed out of the TML. The first guard encloses the die active area. Furthermore the IC includes a second guard ring formed out of the TML. The second guard ring encloses the first guard ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.