Apparatus and method for burn-in and testing of devices with solder bumps or preforms
US5880590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | May 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/13
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Temporary connections are formed to a flip-chip style chip having solder bumps or preforms protruding therefrom for testing and burn-in while avoiding distortion of the solder bumps or preforms and avoiding wear and damage to a test or burn-in jig such as a ball grid array by the use of a preferably resilient bucketed interposer which includes recesses which have a depth greater than the protrusion of the solder bumps or preforms and, preferably are narrowed at one side to a tear-drop shape. Metallization in the recesses and contacts on the interposer which mate with the test or burn-in jig are preferably textured with dendrites to be self-cleaning. A bevelled tongue and groove arrangement translates a slight compressive force to a slight shearing force between the interposer and the chip to ensure good connections to the protruding solder bumps or preforms on the chip. Any deformation of the solder bumps or preforms thus tends to only improve accuracy of positioning of the solder bumps or preforms and avoids solder voiding due to compression distortion of the solder bumps or preforms. Full burn-in and functional testing can then identify "known good" chips or dies before package c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.