Self adjusting pre-charge delay in memory circuits and methods for making the same
US5881008A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Sep 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embedded memory device structure, and a method for making the embedded memory device structure having self adjusting pre-charge delay characteristics. The method includes selecting a desired memory array having a dummy column of cells. Coupling a pre-charge detect circuit to the dummy column of cells. The pre-charge detect circuit is configured to measure an activation and pre-charge response time of cells contained within the dummy column of cells. Transferring the activation and pre-charge response time to an address transition detect unit. The method further includes generating a custom clock timing signal in response to the activation and pre-charge response time of cells contained within the dummy column of cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.