Logic circuit having error detection function and processor including the logic circuit
US5881078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Soft errors generated at an active time are reduced by adding a small-scale circuit to a high performance LSI, such as a processor without reducing the performance of the circuit. The processor has individual logic circuits each having a plurality of stages of logic gates for outputting true signals and complement signals for the individual logic gates. A latch circuit latches the true and complement signals of the logic circuits separately and a compare circuit detects for an error by comparing the true and complement output signals of the logic circuits to determine if they are at the same logical signal level or not, just upstream of the latch in which the individual true and complement output signals of the final logic circuit stages are individually latched. When the compare circuit detects an error because the true and complement output signals are at the same logical signal level, a recovery process is executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.