System and method for clock management
US5881271A · kind A · utility
14Cited by
6References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system in accordance with the invention comprises a first clock input for carrying a clock input signal having first clock cycles, a clock output for carrying an output clock signal having cycles which are synchronous with the first clock cycles, and programmable delay means. Programmable delay means receives the clock input signal, and generates the output clock signal which is delayed from the input by at least a programmable delay and where the programmable delay causes the output clock signal to be synchronous with the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.