Method of forming a self-aligned, sub-minimum isolation ring
US5882977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Oct 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An isolation method in which an isolation ring is formed to isolate a semiconductor device from other semiconductor devices on a common substrate. The method is suitable for isolating bipolar devices from CMOS or other devices formed on the same substrate and for preventing base current from being injected into the substrate. The method starts with a substrate having a buried sub-collector and a first isolation region that surrounds the portion of the surface to contain the semiconductor device. The first isolation region extends only part of the distance from the surface towards the buried sub-collector. Layers of polysilicon and dual-tone resist are applied, and a first mask is used with an opaque area aligned over the portion of the surface to contain the semiconductor device. The edge of the opaque region terminates above the first isolation region. After exposure, the properties of the dual-tone resist allow a narrow sub-minimum width trench to be removed from the resist to define an isolation ring. Ion implantation is then used to form a second isolation region extending to the sub-collector to form the isolation ring. Blanket exposure of the resist and further processing all…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.