Stephen A. St. Onge
32Patents
10h-index
50Co-inventors
74Inventor score
Filing activity: Oct 3, 1997 → Jul 30, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6900519B2 | Diffused extrinsic base and method for fabrication | Electricity | 96 | Expired |
| US6600199B2 | Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity | Electricity | 34 | Expired |
| US6258695A | Dislocation suppression by carbon incorporation | Electricity | 28 | Expired |
| US6452251B1 | Damascene metal capacitor | Electricity | 26 | Expired |
| US6812545B2 | Epitaxial base bipolar transistor with raised extrinsic base | Electricity | 22 | Expired |
| US6476483B1 | Method and apparatus for cooling a silicon on insulator device | Emerging Cross-Sectional Technologies | 20 | Expired |
| US7002221B2 | Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same | Electricity | 15 | Expired |
| US6096618A | Method of making a Schottky diode with sub-minimum guard ring | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6121122A | Method of contacting a silicide-based schottky diode | Electricity | 13 | Expired |
| US7253096B2 | Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same | Electricity | 10 | Expired |
| US6507063B2 | Poly-poly/MOS capacitor having a gate encapsulating first electrode layer | Electricity | 10 | Expired |
| US7709930B2 | Tuneable semiconductor device with discontinuous portions in the sub-collector | Electricity | 9 | Expired |
| US6597050B1 | Method of contacting a silicide-based schottky diode and diode so formed | Electricity | 8 | Expired |
| US6617220B2 | Method for fabricating an epitaxial base bipolar transistor with raised extrinsic base | Electricity | 8 | Expired |
| US5882977A | Method of forming a self-aligned, sub-minimum isolation ring | Electricity | 8 | Expired |
| US6384468B1 | Capacitor and method for forming same | Electricity | 8 | Expired |
| US6440811B1 | Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme | Electricity | 6 | Expired |
| US6448124B1 | Method for epitaxial bipolar BiCMOS | Electricity | 6 | Expired |
| US6329690A | Method and apparatus to match semiconductor device performance | Electricity | 6 | Expired |
| US8466501B2 | Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET | Electricity | 6 | Active |
| US7701015B2 | Bipolar and CMOS integration with reduced contact height | Electricity | 5 | Expired |
| US7550787B2 | Varied impurity profile region formation for varying breakdown voltage of devices | Electricity | 3 | Expired |
| US6869854B2 | Diffused extrinsic base and method for fabrication | Electricity | 3 | Expired |
| US8640077B1 | Capturing mutual coupling effects between an integrated circuit chip and chip package | Physics | 3 | Active |
| US6833299B2 | Method of fabricating a stacked poly-poly and MOS capacitor using a sige integration scheme | Electricity | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.