Edge wrap-around protective extension for covering and protecting edges of thick oxide layer
US5883410A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jun 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/111
Abstract
The present invention discloses a power transistor disposed on a substrate. The power device includes a core cell area comprising a plurality of power transistor cells each having drain and a source. Each of the power transistor cells further having a polycrystalline silicon gate formed on the substrate as part of a polycrystalline silicon gate layer overlaying the substrate. The polycrystalline silicon gate layer includes a plurality of polycrystalline gate-layer-extension extending to gate contact areas for forming gate contacts with a contact metal disposed thereon. The power transistor further includes a plurality of contact-metal-resistant pad each includes a thick oxide pad disposed below the gate contact areas underneath the polycrystalline gate layer extension whereby the contact-metal resistant pads resists the contact metal from penetrating therethrough and short to the substrate disposed thereunder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.