Low gate resistance high-speed MOS-technology integrated structure
US5883412A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 13, 1995 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jul 13, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A high-speed MOS-technology power device integrated structure includes a plurality of elementary functional units formed in a lightly doped semiconductor layer of a first conductivity type, the elementary functional units including channel regions of a second conductivity type covered by a conductive insulated gate layer including a polysilicon layer; the conductive insulated gate layer also including a highly conductive layer superimposed over the polysilicon layer and having a resistivity much lower than the resistivity of the polysilicon layer, so that a resistance introduced by the polysilicon layer is shunted with a resistance introduced by the highly conductive layer and the overall resistivity of the conductive insulated gate layer is lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.