FPGA architecture with repeatable titles including routing matrices and logic matrices
US5883525A · kind A · utility
360Cited by
36References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Oct 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.