Hierarchical interconnect for programmable logic devices
US5883526A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Apr 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hierarchical interconnect structure between logic elements, logic array blocks and global interconnects in a programmable logic device is disclosed. The present invention provides a first group of local interconnect lines that couple to outputs of more than one logic element in a block, and a second group of local interconnect lines that are divided into independent segments coupled to a subset of the logic elements in a block. By eliminating the one-to-one correspondence between the number of logic elements in a logic array block and the number of local interconnect wires, the present invention makes possible the inclusion of more logic element in one block in an area efficient manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.