Memory block select using multiple word lines to address a single memory cell row
US5883826A · kind A · utility
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A highly suitable power conservation technique involves extending multiple word lines over a memory array row and connecting a portion of the memory cells of the memory array row to each of the word lines. Power is supplied only to the portion of the memory cells that is accessed, eliminating the static power consumption of the non-accessed memory cells. By connecting multiple word lines to select a portion of a memory row, a column address of the memory is mapped into a row decode space. Multiple metal layers in a complex integrated circuit may be exploited to form cache block select lines using multiple word lines per cell row. A storage includes a plurality of storage cells arranged in an array of rows and columns, a plurality of bit lines connecting the array of storage cells into columns, and a plurality of word lines connecting the array of storage cells into rows. The plurality of word lines include multiple word lines for a single row of the plurality of rows so that multiple portions of the storage cells in the single row are addressed by corresponding multiple word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.