Electrically erasable and programmable non-volatile storage location
US5883832A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1998 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Jan 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Electrically erasable and programmable non-volatile memory cell, which is formed with only one MOS transistor which is formed by a source-channel-drain junction, semi conductor substrate (1) of a first conductivity type has a drain region (2) and a source region (3) of a second conductivity type with a polarity opposite to that of the first conductivity type. A gate electrode (4), which is at a floating potential, is electrically insulated from the drain area (2) by a tunneling oxide (5) and from a channel region (9), which is located between the drain area and the source area (2, 3), by a gate oxide (5; 10). It and extends at least over a part of the channel region (9) and a part of the drain region (2) in the source-channel-drain direction. A control electrode (7) is electrically insulated from the gate electrode (4) by a coupling oxide (8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.