Reading circuit for semiconductor memory cells
US5883837A · kind A · utility
8Cited by
5References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.