Method and apparatus for reducing data transfers across a memory bus of a disk array controller
US5883909A · kind A · utility
181Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1996 |
| Grant date | Mar 16, 1999 |
| Priority date | — |
| Expiry date | Nov 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for transferring data from a first device to a second device connected by a controller having a parity buffer and a memory having a first storage and a second storage is disclosed. The method includes the steps of transferring first data from the first device to the first storage; transferring second data from the first device to the second storage; transferring the first data to the second device and storing the first data in the parity buffer; and determining parity data from the second data and the first data stored in the parity buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.