Integrated circuit having a dummy structure and method of making

US5885856A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Percy V. Gilbert · Austin, US
• Subramoney Iyer · Austin, US
• Bradley P. Smith · Youngstown, US
• Matthew A. Thompson · White Pigeon, US
• Kevin Kemp · Walker, US
• Rajive Dhar · Santa Clara, US

Key dates

• Filing date: Aug 21, 1996
• Grant date: Mar 23, 1999
• Expiry date: Aug 21, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76819
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).