Semiconductor device using dual damascene technology and method for manufacturing the same
US5886411A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Jul 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Trenches are formed in a silicon oxide film, a barrier metal film and tungsten film are formed, and the surface portion is polished to make the surface flat and form interconnection layers of the tungsten film in the trenches. Then, the tungsten film and barrier film are etched to form a stepped portions, a silicon nitride film is formed to fill the stepped portions, and the silicon nitride film is polished to make the surface flat. After this, the silicon oxide film is etched by use of a mask pattern to form contact holes in a self-aligned manner. Then, a silicon nitride film is formed and the surface portions is etched back to form side walls on the side walls of the contact holes and a barrier metal film and tungsten film are sequentially formed to fill the contact holes, then the tungsten film and barrier metal film are polished until the silicon oxide film and silicon nitride film are exposed, and as a result, the surface is made flat.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.