Latch optimization in hardware logic emulation systems
US5886904A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1996 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Sep 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.