Fast calculation method and its hardware apparatus using a linear interpolation operation
US5886911A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Jan 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a fast calculation method and, more particularly, to a fast calculation method and its hardware apparatus using a linear interpolation operation. Primarily, the two existing values of the two given points X and Y intended to proceed the linear interpolation operation are stored in two registers A and B respectively, and then they are added through an adder and the lowest order bit of the sum is discarded to form a mean value. The resulting value discarded from the lowest order bit is then sent to a multiplexer and every bit in the binary representation of the position pointer K is sent to a selection input terminal of the multiplexer in sequence from the highest order bit to the lowest order bit. The resulting value discarded from the lowest order bit is sent back to either one of the two registers A and B in accordance with the digit of the corresponding bit in the binary representation of the position pointer K. The process described above will be repeated several times until the lowest order bit in the binary representation of the position pointer K is sent and finally, the interpolation value of the target point I is one of the resulting values …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.