Semiconductor memory having a hierarchical data line structure
US5886943A · kind A · utility
32Cited by
6References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1997 |
| Grant date | Mar 23, 1999 |
| Priority date | — |
| Expiry date | Sep 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An increase in a dynamic random access memory (DRAM) chip area is minimized by dividing data lines into multiple sections, arranging global data lines parallel to the data lines and placing them in a hierarchical structure. The switches connecting the data lines and the global data lines are arranged separately or in alternate positions to further reduce the chip area. The influence of noise due to the length of data lines is reduced. Sense amplifier drive circuits are controlled to selectively apply voltages to the sense amplifiers depending upon the length of the path from each sense amplifier to a particular memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.