Apparatus and method for unit area composition control to minimize warp in an integrated circuit chip package assembly
US5888630A · kind A · utility
11Cited by
10References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Nov 8, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24942
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a multi-layered structure includes forming first and second layers, patterning the first layer, determining a distribution of material in at least one area of the first layer, and altering the material content of one of the first and second layers in at least one of the first layer area and a corresponding area of the second layer to approximately match the material content of the first layer and second layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.