Electronic device pad relocation, precision placement, and packaging in arrays
US5888884A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 2, 1998 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Jan 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.