Silicide for achieving low sheet resistance on poly-Si and low Si consumption in source/drain
US5889331A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process of forming a semiconductor structure. The process includes patterning a conductive layer with a top surface and opposing sides over an area of a semiconductor substrate, depositing a dielectric layer over the conductive layer, and etching the dielectric layer to form spacer portions adjacent the sides of the conductive layer and to expose the top surface and a portion of the conductive layer. The process may be used to form salicides wherein the thickness of the silicide layer of the conductive layer is greater than the thickness of the silicide layer in the diffusion region of a device. The invention also relates to a semiconductor device that includes a conductive layer with opposing side portions over an active area of a semiconductor substrate and a dielectric spacer adjacent to less than the entire portion of a side portion of the conductive layer. The semiconductor device may be used with a salicide process to yield a silicide layer over the conductive layer that is thicker than the silicide layer in the diffusion regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.