Symmetrical nand gates
US5889416A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 1997 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Oct 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A NAND gate including a pull-down circuit coupled to a pull-up circuit. The NAND gate is configured to drive an output signal to a high logic state at a substantially uniform slew rate regardless of the number of input signals that are in a low logic state. The pull-up circuit may include a plurality of load circuits each coupled to a corresponding one of the plurality of input signals, and a plurality of transistor circuits each comprising a plurality of transistors coupled in parallel with each other and coupled to a corresponding one of the plurality of input signals or a complement of a corresponding one of the plurality of input signals. The plurality of load circuits and the plurality of transistors may each include a p-channel MOS (PMOS) transistor. The NAND gate may be incorporated into a decoder of a synchronous or asynchronous input path circuit to generally reduce the setup and hold time window of the input path circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.