Simon J. Lovett
66Patents
12h-index
25Co-inventors
84Inventor score
Filing activity: Dec 23, 1996 → Aug 12, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6262937A | Synchronous random access memory having a read/write address bus and process for writing to and reading from the same | Physics | 51 | Expired |
| US6100560A | Nonvolatile cell | Physics | 41 | Expired |
| US6069839A | Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method | Physics | 29 | Expired |
| US6920524B2 | Detection circuit for mixed asynchronous and synchronous memory operation | Physics | 26 | Expired |
| US6181621A | Threshold voltage mismatch compensated sense amplifier for SRAM memory arrays | Physics | 26 | Expired |
| US7034507B2 | Temperature sensing device in an integrated circuit | Electricity | 25 | Expired |
| US6278295A | Buffer with stable trip point | Electricity | 20 | Expired |
| US7272065B2 | Compensated refresh oscillator | Physics | 17 | Expired |
| US6385128B1 | Random access memory having a read/write address bus and process for writing to and reading from the same | Physics | 16 | Expired |
| US6292403A | Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method | Physics | 15 | Expired |
| US6262936A | Random access memory having independent read port and write port and process for writing to and reading from the same | Physics | 14 | Expired |
| US6690606B2 | Asynchronous interface circuit and method for a pseudo-static memory device | Physics | 13 | Expired |
| US5889416A | Symmetrical nand gates | Electricity | 11 | Expired |
| US9508409B2 | Apparatuses and methods for implementing masked write commands | Physics | 11 | Active |
| US7640413B2 | Detection circuit for mixed asynchronous and synchronous memory operation | Physics | 11 | Active |
| US7320049B2 | Detection circuit for mixed asynchronous and synchronous memory operation | Physics | 9 | Expired |
| US6097222A | Symmetrical NOR gates | Electricity | 8 | Expired |
| US10734067B1 | Memory device latch circuitry | Physics | 8 | Active |
| US7408813B2 | Block erase for volatile memory | Physics | 7 | Active |
| US11664063B2 | Apparatuses and methods for countering memory attacks | Electricity | 7 | Active |
| US10403389B2 | Array plate short repair | Physics | 7 | Active |
| US6845054B2 | Zero power chip standby mode | Physics | 7 | Expired |
| US6538466B1 | Buffer with stable trip point | Electricity | 6 | Expired |
| US10957365B2 | Setting local power domain timeout via temperature sensor systems and methods | Emerging Cross-Sectional Technologies | 5 | Active |
| US7106637B2 | Asynchronous interface circuit and method for a pseudo-static memory device | Physics | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.