Apparatus and method for improving the noise immunity of a dynamic logic signal repeater
US5889417A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | May 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a precharge signal. The complementary dynamic logic circuit configuration, transistor sizing, and the use of a precharge driver results in a signal transition trip point for the precharge signal on the output node that is substantially equivalent to the signal transition trip point of a static logic circuit. Thus, the dynamic logic signal repeater has improved noise immunity. An evaluation locking transistor is connected to the complementary dynamic logic circuit and the output node. The evaluation locking transistor prevents the charging of the output node during a dynamic logic evaluation period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.