Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM
US5890192A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1996 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Nov 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.