Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5890200A · kind A · utility
38Cited by
22References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 4, 1997 |
| Grant date | Mar 30, 1999 |
| Priority date | — |
| Expiry date | Apr 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for maintaining cache coherency for snoop operations includes a snoop scheduler coupled to receive addresses from a system bus. The snoop scheduler utilizes a content addressable memory array. The snoop scheduler determines if snoop operations are orthogonal and schedules one or more out-of-order and at least partially overlapping snoop operations. Determining which snoop operations are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.