Getterer for multi-layer wafers and method for making same
US5892292A · kind A · utility
17Cited by
15References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/912
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A getterer structure for dielectrically isolated wafer structures such as bonded wafers. The getterer is a layer of polysilicon along the sidewalls of semiconductor regions isolated from each other by trenches. The polysilicon may be doped. The polysilicon is oxidized and polysilicon deposited to fill voids in the trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.